1. Field of the Invention
This invention relates to a semiconductor data storage apparatus, on which a memory device, such as a flash memory, is mounted which enables data to be collectively erased from the overall memory region or each block in the memory thereof, and, more particularly to shortening the time required to erase or program (write) data.
2. Description of the Related Art
FIG. 7 is a block diagram which schematically illustrates the structure of a conventional semiconductor data storage apparatus including a collectively-erasable memory device. As an apparatus of the foregoing type, a flash memory card including a plurality of flash memory devices is available. The foregoing semiconductor storage apparatus is connected to a control unit (not shown) so that data is, under control of the control unit, read, programmed (written) and collectively erased. A flash memory card serving as a portable storage medium is attachably/detachably connected to a terminal unit through a connector so that data is, similarly to the foregoing apparatus, read, programmed and collectively erased under control of the terminal unit.
In a semiconductor storage apparatus 10 shown in FIG. 7, reference numeral 1 represents a input/output signal line group for receiving a variety of control signals, software commands, addresses and data to be written, which are supplied from the control unit, and for transmitting stored data to the control unit, the signal lines being connected to the control unit. Reference numeral 2 represents a memory portion which consists of a plurality of collectively-erasable memory devices 2a to 2k. Reference numeral 3 represents a decoder for selectively activating each memory device in the memory portion 2 in response to a signal supplied from the input/output signal line group 1. Each of the memories 2a to 2k of the memory portion 2 comprises a collectively-erasable flash EEPROM. The memory device of the foregoing type is exemplified by 5M28F101P, FP, J, VP, RV or 5M28F102P, FP, J, VP, RV or the like. The decoder 3 comprises, for example, 74ALS138.
In the input/output signal line group 1, reference numeral 1a represents a lower address signal line group (A.sub.0 to A.sub.n) for addressing each of the memory devices 2a to 2k. Reference numeral 1c represents an output enable signal line (OE bar) for bringing the memory device to a data readable state. Reference numeral 1d represents a write enable signal line (WE bar) for bringing the memory device to a state where data and a software command can be written. Reference numeral 1f represents a data bus (DA) through which data to be stored or stored data is input to/output from the memory device and through which a software command is input to the memory device. The signal lines 1a, 1c, 1d and 1f are connected to the memory devices 2a to 2k. Reference numeral 1b represents an upper address signal line group (A.sub.n+1 to A.sub.m) for specifying a memory device in the memory portion 2 that is activated. Reference numeral 1e represents an enable signal line (CE bar) for activating the decoder 3, that is, the semiconductor storage apparatus 10. The signal lines 1b and 1e are connected to the decoder 3. Reference numerals 3a to 3k represent memory selection signal lines (S bar). The decoder 3 supplies, through the memory selection signal lines 3a to 3k, a memory selection signal for activating a predetermined memory device in response to the signal supplied through the upper address signal line group 1b. Vcc represents a power supply source for supplying normal operating voltage to the memory device, and Vpp represents a power supply source for switching and supplying a voltage required when data is read from the memory device or required when data is programmed or erased. Also the voltages Vcc and Vpp are supplied from the control unit (not shown). Note that the signal lines and the signals to be transmitted through the signal lines are given the same reference numerals.
The operation of the circuit in the semiconductor storage apparatus 10 shown in FIG. 7 will now be described, the circuit being a negative logic circuit.
Initially, the operation of the flash EEPROM that constitutes each of the memory devices 2a to 2k of the memory device 2 will be schematically described. Each of the memory devices 2a to 2k comprising the flash EEPROM has two operation modes consisting of a read only mode and a read/write mode that can be switched in accordance with the voltage level of the power supply source Vpp. In a case where the power supply source Vpp is at a low level of VppL (for example, 5 V), the read only mode is set in which data can be read. If the power supply source Vpp is at a high level of VppH (for example, 12 V), the read/write mode is set in which data can be read, programmed and erased.
When each of the memory devices is in the read only mode because the power supply source Vpp has been set to the low level VppL, the read mode is realized by setting the memory selection signals (S bar) 3a to 3k and the output enable signal (OE bar) 1c to the low level and by setting the write enable signal (WE bar) 1d to the high level. Thus, stored data appears on the data bus 1 f in accordance with the lower address signals (A.sub.0 to A.sub.n).
When the power supply source Vpp has been set to the high level VppH and thus the read/write mode has been set, the write mode is realized by setting the write enable signal (WE bar) 1d to the low level in a state where the level of the memory selection signal (S bar) is low and that of the output enable signal (OE bar) 1c is high. Thus, a software command can be input through the data bus 1f. In accordance with the content of the software command, data can be programmed or erased. Each memory device has a command latch circuit, an internal control circuit (not shown, respectively) and the like. The software command latched by the command latch circuit serves as an input for the internal control circuit. Thus, the output from the internal control circuit causes programming or erasure.
The foregoing fact will now be described in terms of the software command. When the power supply source Vpp is at the low level VppL, the content of the command latch circuit is automatically set to a content that indicates the read only mode. Therefore, writing of a software command is inhibited. When the power supply source Vpp is on the high level VppH, the memory device is brought to the read/write mode as described above. Therefore, the operation of the memory device is selected by writing a specific software command in the command latch circuit.
The total operation of the semiconductor data storage apparatus 10 will now be described. The semiconductor storage apparatus 10 is connected to the control unit (not shown) through the input/output signal line group 1 as described above and is operated under control of the control unit. The semiconductor data storage apparatus 10 is activated when it receives a low level enable signal (CE bar) 1e. When the semiconductor storage apparatus 10 has been activated, the decoder 3 supplies the low level memory selection signal (S bar) to a predetermined memory device in the memory portion 2 in accordance with the upper address signals (A.sub.n+1 to A.sub.m) 1b to activate the memory device. That is, when the upper address signal 1b for selecting, for example, the memory device 2a has been supplied, the memory selection signal 3a is made to be the low level and the residual memory selection signals 3b to 3k are made to be the high level. The selected memory device is brought to the read only mode or the read/write mode in accordance with the level of the power supply source Vpp. Thus, the memory device is operated in response to any of a variety of control signals, software commands, addresses and data supplied by the control unit.
The operation of each of the memory devices 2a to 2k in the read only mode realized by setting the power supply source Vpp to the low level VppL will now be described. A consideration is performed in a case where data in the memory device 2a is read. When a predetermined upper address signal 1b is supplied, the decoder 3 lowers the level of only the memory selection signal 3a to selectively activate the memory device 2a. Since the power supply source Vpp has been set to the low level VppL, the memory device 2a has been set to the read only mode. Therefore, setting of the output enable signal (OE bar) 1c to the low level and setting of the write enable signal (WE bar) 1d to the high level bring the mode to the read mode as described above. As a result, data stored in the data bus 1f appears in accordance with the lower address signals (A.sub.0 to A.sub.n).
A description is given of the operation of each of the memory devices 2a to 2k in the read/write mode realized by setting the power supply source Vpp to the high level VppH, in particular, in the write mode in which data is programmed or erased. FIG. 8 illustrates a portion of a flow chart of an operation of erasing data in each memory device, which is a flash EEPROM, to be performed in the write mode. FIG. 9 illustrates a portion of a flow chart of a programming operation.
An operation of erasing data from the memory device 2a or programming data in the same will now be described. The operation to be performed until the memory device 2a is selectively activated is the same as the operation to be performed in the read only mode. Since the power supply source Vpp has been set to the high level VppH, the memory device 2a is in the read/write mode. Therefore, by setting the write enable signal (WE bar) 1d to the low level and by setting the output enable signal (OE bar) 1c to the high level, the memory device 2a is brought to the write mode. Thus, writing of a software command on the included command latch circuit (not shown) is enabled.
Initially, an operation to be performed when data in the memory device 2a is erased will now be described with reference to FIG. 8. When an erase command, which is a software command, has been written in the command latch circuit of the memory device 2a by the control unit, the memory device 2a is brought to the erase mode. The erase command is a command for collectively erasing all data bytes in the memory device. For example, a cycle of writing "20H" in the command latch circuit is repeated two times (steps S1 and S2). The reason for repeating the cycle two times is that an erroneous erasure must be prevented. Then, the erasing operation is performed for about 10 ms so that all data items in the memory device 2a are erased. The period of the foregoing erasing operation is the waiting time (step S3). After the erasing operation has been completed, an erase confirmation command (for example "AOH") for confirming that data has been erased is written (step S4). Then, the time of about 6 .mu.s passes during which the memory device 2a is switched to the read mode, the foregoing time being waiting time (step S5). Then, the control unit reads data from the memory device 2a and a confirmation is performed as to whether all data items, which have been read, are "FFH" so that whether data has been erased is confirmed (step S6).
In a case where data items in the memory devices 2a to 2k are sequentially erased similar to the operation above, the upper address signal 1b is switched to cause the decoder 3 to select a predetermined memory device. Thus, data is erased by a similar procedure and the procedure is repeated.
The operation to be performed when data is programmed on the memory device 2a will now be described with reference to FIG. 9. When a program command, which is a software command, has been written in the command latch circuit of the memory device 2a, the memory device 2a is brought to the program mode. In accordance with the program command, "40H" is initially written in the command latch (step S1), and then data for one byte to be programmed and its address are written (step S2). Then, programming of the data is executed for about 10 .mu.s so that data of one byte is programmed in the addressed portion. The foregoing period is the waiting time (step S3). Then, a program confirmation command (for example "COH") is written in order to confirm that the data has been programmed (step S4). The ensuing time is about 6 .mu.s during which the memory device 2a is switched to the read mode and the foregoing time is the waiting time (step S5). Then, the programmed data in the memory device 2a is read by the control unit and a confirmation is made as to whether the data has been programmed correctly (step S6). As a result of the foregoing steps S1 to S6, data of one byte is programmed and the confirmation of programming is performed. The foregoing cycle is repeated by a number that corresponds to the number of bytes of the data to be programmed.
In a case where data items are sequentially programmed in the memory devices 2a to 2k similarly to the above operation, the upper address signal 1b is switched so that a predetermined memory device is selected by the decoder 3. Therefore, data is programmed by a similar procedure and this operation is repeated.
The conventional semiconductor storage apparatus having the foregoing structure, at the time of collectively erasing or programming data, involves a problem in that the time during execution of the command after the command has been written is a waiting time, and the time is elongated in proportion to the capacity of the memory, that is, the number of the memory devices. Thus, the time required to program or erase the data is elongated excessively.